Refilling a missed TLB entry, now with special sauce

Jeremy and Muli remind me that x86-class CPUs refill a missed TLB entry in hardware. That’s what I get for rambling at midnight! On these CPUs, the hardware walks the page tables directly when a miss occurs. The operating system still gets involved during context switches, to keep the page tables and TLB consistent; and it also shoots down individual TLB entries when messing with memory mappings. In my puny and lame defence, most RISC CPUs (you know, the ones that nobody uses any more) trap to the operating system when a TLB miss occurs, and do the refilling in software. (A few, like SPARC, have an auxiliary cache that’s bigger than the TLB, to speed up software reloads.) Jeremy also asked if a TLB lookup and L1 cache lookup can happen in parallel. As he points out, they can’t if the L1 cache contains physical addresses (which is called physical indexing). L1 caches that are virtually indexed do show up, though, because they allow the TLB lookup to occur in parallel with the L1 cache lookup. The machinery is more complicated due to the need to account for a single physical address having multiple virtual addresses mapping to it. As far as I know, only the HP PA and AMD Athlon, both of which are defunct, have virtually indexed caches.